Empowering Smarter Wireless: FPGA-Accelerated Deep Learning for RIS Configuration

Contributing experts

As wireless connectivity becomes ever more essential, the need for smarter, more adaptive communication infrastructure is clear. One of the most promising technologies leading this next wireless generation (6G) is the Reconfigurable Intelligent Surface (RIS)—a system capable of shaping the wireless environment itself.

At HTEC, we’ve collaborated with leading research institutions to explore how deep learning and reconfigurable hardware can help unlock the full potential of RIS in real-world applications. This article highlights our joint effort with the University of Granada (UGR), specifically with the Smart and Wireless Applications and Technologies (SWAT) Research Group, which developed the RIS hardware platform, and the DiTEC Research Group, with whom we co-designed and implemented a neural network that enables real-time RIS configuration on energy-efficient FPGA hardware.

A 2-bit Reconfigurable Intelligent Surface developed by the SWAT Research Group

What is a Reconfigurable Intelligent Surface?

Unlike traditional fixed antennas, RIS can act like “smart mirrors,” dynamically controlling how wireless signals are reflected.  This makes RIS a powerful tool in future 6G systems, enabling better coverage, reduced interference, and dynamic reconfigurability of the wireless environment. However, to be effective in real-time, RIS devices must be continuously reconfigured based on changing conditions like user movement or signal fading. Traditional optimization algorithms for this task are too slow and computationally heavy for edge deployment—especially in constrained environments like IoT nodes or embedded network infrastructure.

A Joint Research Effort: From ML concept to hardware implementation

The RIS hardware used in this project was developed by the SWAT Research Group, a team with expertise in electromagnetic design and wireless systems. Their prototype features a 15×15 array of binary programmable elements—each capable of applying a 0° or 180° phase shift. While simple in theory, orchestrating this surface to steer signals effectively is a complex optimization task.

To train a model that could predict optimal configurations, SWAT also generated a custom dataset containing all possible configurations. Each data point pairs a UV-mapped representation of a desired redirection angle with the corresponding optimal binary configuration for the RIS. UV-mapping allows us to encode direction data into a 2D color image—perfectly suited for convolutional neural networks (CNNs), which excel at extracting patterns from spatial data.

For the hardware implementation, we worked alongside DiTEC Research Group, who specialize in algorithm deployment on reconfigurable hardware. HTEC then developed and implemented an FPGA-friendly CNN to predict RIS configurations in real time.

Deep Learning for Real-Time RIS Configuration

At the core of the solution is a compact, efficient CNN that maps the desired redirection (encoded as a UV image) to a binary mask representing the optimal RIS configuration. The network is trained as a classification problem—each output bit corresponding to one of the 225 RIS elements.

To improve generalization and accelerate convergence, a custom loss function that tolerates multiple equivalent configurations was used, recognizing that many phase arrangements can achieve the same beam direction. This approach improved robustness and made the model better suited for deployment outside of a lab environment.

Despite its lightweight architecture, the model delivered excellent accuracy on synthetic and experimental data, achieving reliable signal redirection predictions across a wide variety of conditions.

From Lab to Hardware: FPGA Deployment

To move beyond proof-of-concept and into real-world deployment, we focused on implementing the model on a Field Programmable Gate Array (FPGA). These devices allow for custom data paths and precise resource control, making them ideal for low-latency, power-constrained environments where RIS might be deployed—such as on access points, base stations, or smart infrastructure.

Working together with DiTEC, we:

  • Quantized the model to 8-bit fixed-point precision, reducing resource usage.
  • Used High-Level Synthesis (HLS) to translate the neural network into FPGA logic blocks.
  • Tailored the implementation to minimize inference latency.

The results make a compelling case: our FPGA implementation achieved a 20× speedup over a conventional GPU and outperformed a Google Coral Edge TPU by 3× in latency. This opens the door for edge-native, real-time RIS reconfiguration—something previously considered too resource-intensive.

Why This Matters

As RIS becomes integral to future wireless systems, the ability to configure it rapidly and efficiently is paramount. HTEC’s joint research with SWAT and DiTEC demonstrates a complete end-to-end pipeline—from RIS design and simulation to deep learning optimization and hardware deployment.

Crucially, this pipeline is scalable and extensible. While our results correspond with a prototype that uses a 1-bit phase control per RIS cell, the same techniques can be extended to:

  • Multi-bit configurations, for finer-grained control over wave propagation. The SWAT team already have a fully functional prototype of a 2-bit RIS device.
  • Online learning, allowing real-time adaptation in changing environments.
  • Graph Neural Networks (GNNs), to better model spatial relationships between cells.
  • Direct angle-to-mask inference, replacing UV maps with simpler inputs for deployment simplicity.

Through this project, we’ve not only shown that RIS control is feasible on constrained hardware, but that it’s also ready for real-world, scalable deployment. As illustrated, the integration of RIS and AI forms a foundational pillar for 6G, promising smarter, greener, and more resilient networks that can meet the evolving needs of industries and consumers alike.

Final Thoughts

This work is the result of a strong collaboration between industry and academia—each contributing a piece of the puzzle. While SWAT brought cutting-edge RIS hardware design, HTEC and DiTEC contributed deep AI and FPGA expertise, working together to drive the integration, validation, and deployment of the system with a focus on real-world constraints and scalability.

By combining machine learning with reconfigurable hardware, we’re paving the way for intelligent wireless environments that can adapt in real time—unlocking faster, more reliable, and more energy-efficient communication for the next generation of devices. Learn how HTEC leverages AI and emerging technologies to create impact across industries and create smarter, more connected, and future-ready solutions. To further explore the solution showcased above, read the full study here.

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